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february 98 42 1726 00 this is preliminary information on a product in development or undergoing evaluation. details are subject to change without notice. ST18-AU1 six-channel dolby ac3/mpeg2 audio decoder preliminary data features n single chip multi-function audio decoder able to decompress dolby ac-3, mpeg-1 and mpeg-2 audio streams. n maximum 5.1 channel dolby ac-3 decoding to 2 channel mixed down output with dolby surround compatible or karaoke capable option. n variable bit rate mpeg-1 layer ii audio decoding, and mpeg-2 multi-channel audio decoding for karaoke capable application. n input data rates n up to 448 kbits/s for ac-3 decoder n up to 912 kbits/s for mpeg-1 or mpeg-2 audio decoder n supports up to 8 channel dvd linear pcm input at max rate of 6.144 mbits/s down-mixing and/ or sub-sampling to 2 to 6 channels. n accepts mpeg-1 or dvd/mpeg-2 pes input packets. n programmable d950 core n system time clock provides a/v synchronization and pts packet extraction. n automatic error concealment on crc or synchronization error. n 6 channel pcm audio output at 16/18/20/24 bit. sampling rate of 32/44.1/48/96 khz. n two on-chip plls providing full circuit operation with only one external 27 mhz clock. n i 2 c interface for host control n multi-format i 2 s serial data input port and decoded audio pcm output port. n iec-958 (s/pdif) formatter and transmitter for dolby ac-3, mpeg audio bit stream, or audio pcm. n dedicated hardware for emulation and test, ieee 1149.1 (jtag). n 3.3v power supply, i/o's 5v tolerant, 0.35 m m hcmos6 technology. n 160 pin pqfp package applications n digital video disc (dvd) player n digital tv (dbs/dvb) receiver n pc multimedia n consumer digital audio interrupt controller clocks and timers i 2 c host interface 2 input serial interface iec-958 (s/pdif) output 16k program memory 3 output serial interface d950 dsp core 24k data memory dma controller emulation unit and tap bus switch unit
2/87 table of contents 4 1 introduction ...................................................... 5 2 pindescriptions ................................................... 7 3 functionaloverview ............................................. 12 4 hostinterface ................................................... 16 4.1 hostinterfaceregisters ................................... 16 4.2 listofhostcommands ...................................... 19 5 inputserialinterface............................................ 25 5.1 input serial interface registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.2 input fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....................... 27 5.2.1 input fifo registers . . . . . . . . . . . . . . . . . . . ..................... 27 6 inputandoutputbuffers ........................................ 29 6.1 inputbuffer ................................................. 29 6.2 outputbuffer ............................................... 29 6.2.1 input and output buffer registers . . . . .......................... 29 7 outputserialinterface-pcmoutput ............................ 31 7.1 outputserialinterfaceregisters .......................... 31 8 interrupt controller . . . . . . . . . . . . . . . . . . . ........................ 34 8.1 interrupt controller registers . . . . . . . . .................... 35 9 dmacontroller .................................................. 40 9.1 dmaoperation ............................................... 40 9.2 dmaregisters ............................................... 41 9.2.1 address registers . . . . . . . . . . . . . . . . . . ........................ 41 9.2.2 counting registers . . ....................................... 41 9.2.3 control registers . .......................................... 42 10 iec-958 transmitter . . . . . . . . ....................................... 44 10.1 iec-958 transmitter registers . . . . . . . . . . . . . . . . . . . . . .......... 44 11 memory .......................................................... 46 11.1 internalmemoryresource .................................. 46 11.2 i-memory bus extension - direct and through bsu . . . . . . . . . . . 47 11.3 x-memory bus extension - direct and through bsu ........... 47 11.4 y-memory bus extension through bsu . . . . . . . . . . ............. 47 12 busswitchunit................................................... 48 12.1 bsucontrolregisters ...................................... 48 13 clocks and timers unit . . . . . . . . . . ................................. 51 13.1 operation ................................................... 51 1
3/87 table of contents 13.1.1 audio clock prescaler . . . .................................... 51 13.2 clocks and timers registers . . . ............................. 52 14 jtagieee1149.1testaccessport ................................. 55 15 emulationunit ................................................... 56 16 d950core ......................................................... 58 16.1 d950coreregisters.......................................... 60 17 yspacememorymapping ......................................... 61 17.1 memorymap ................................................. 61 17.2 clocks and timers registers . . . ............................. 62 17.3 iec-958 transmitter (s/pdif output) registers . . . ............. 63 17.4 pcmregisters ............................................... 63 17.5 input/output buffer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 17.6 serialinput1registers ..................................... 64 17.7 serialinput0registers ..................................... 64 17.8 hostinterfaceregisters ................................... 64 17.9 busswitchunitregisters ................................... 64 17.10pllregisters ................................................ 65 17.11dmacontrollerregisters .................................. 65 17.12 interrupt controller registers ............................ 66 17.13d950corecontrolregisters ................................ 66 17.14 data and program memory mapping . . . . . . . . . . . . . . . . .......... 67 18 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . ............. 68 18.1 dcabsolutemaximumratings................................ 68 18.2 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 18.3 accharacteristics .......................................... 69 18.3.1 clocks electrical characteristics . . ............................. 72 18.3.2 e-bus (i direct extension) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 18.3.3 e-bus (x direct extension) . . . . . . . . . . . . . . . .................... 74 18.3.4 e-bus (i bsu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ............. 75 18.3.5 e-bus (x bsu) . . .......................................... 76 18.3.6 e-bus (y bsu) . . .......................................... 77 18.3.7 d950 control . . . . . . . . . . . . . ................................. 78 18.3.8 i2c host interface . . . . . .................................... 79 18.3.9 pcm and spdif .......................................... 80
4/87 table of contents 4 18.3.10 i2s data input 0 . .......................................... 81 18.3.11 i2s data input 1 . .......................................... 82 19 ST18-AU1 package specifications . . . . . . . . . . ....................... 83 19.1 ST18-AU1 package pinout . .................................... 83 19.2 160pinpqfppackagedimensions ............................. 84 20 deviceid.......................................................... 86 21 ordering information . . . . . . . . . . . . . . . . . ........................... 86
5/87 ST18-AU1 1 introduction the ST18-AU1 is a single-chip multi-function audio processor for dolby ac-3, mpeg-1/ mpeg-2 layer-i/ii audio encoded bitstreams, and dvd linear pcm. it is capable of decoding up to 5.1 channels of input dolby ac-3 or mpeg-2 multi-channel encoded audio, and down mixing to 2 channels of pcm output audio. maximum input data rates for dolby ac-3 bitstream and mpeg-2 audio bitstream are 448 kbits/s and 912 kbits/s respectively. it also supports up to 8 channel linear pcm input with by-pass, down-sampling, and down-mixing function. the linear pcm multi-channel input modes available are: ? 48 khz/16-bit up to 8 ch @ max 6.144 mbps ? 48 khz/20-bit up to 6ch @ max 5.760 mbps ? 48 khz/24-bit up to 5ch @ max 5.760 mbps ? 96 khz/16-bit up to 4ch @ max 6.144 mbps ? 96 khz/20-bit up to 3ch @ max 5.760 mbps ? 96 khz/24-bit up to 2ch @ max 4.608 mbps ? 44.1 khz/16-bit 2ch (cd-da). the input bitstream is taken from the multi-format serial input, and decoded according to the selected mpeg-1, mpeg-2 (in the case of karaoke capable mode), ac-3 decoder or linear pcm processor. a packet demux de-multiplexes the input if it is mpeg-1 or dvd/mpeg-2 pes packetized. for an input bitstream with more than 2 encoded audio channels, the decoded channels are mixed down to 2 channels with the dolby surround compatible or karaoke capable option, and outputted through a multi-format serial output port. the input ac- 3, mpeg bitstream, or decoded pcm can be outputted through an iec-958 (s/pdif) formatter/transmitter. the ac-3 or mpeg s/pdif output bitstream is delayed and synchronized with the output decoded pcm. the karaoke capable mode defined in dolby ac-3 or dvd to allow the multi-channel audio stream to convey channels designed as l, r (2-ch stereo music), m (guide melody), and v1, v2 (one or two vocal/supplementary tracks) are supported. this karaoke capable decoder allows the user to choose to have the decoder reproduce any of the guide melody and vocal/ supplementary channels. centre and surround mix levels either controlled by the user or within the bitstream are used to down mix the m channel and the v1, v2 channels respectively. the selectable linear pcm processor functions are: ? down-mixing to 2 channels, ? down-sampling for 96khz to 48khz, ? noise shaped quantization for 24-bits or 20-bits to 16-bits. depending on the application, the decoded pcm audio output is selectable to be 16, 18, 20 or 24 bits, and the sampling rates of the pcm output are 32 khz, 44.1 khz, 48 khz or 96 khz. external a/v synchronization can be assisted by the system time clock (stc) within the timer and the pts extracted from the packetized input. a serial i 2 c interface to host 2
6/87 ST18-AU1 microcontroller is provided to allow ST18-AU1 operation control, bitstream information and internal status access. a typical dvd back-end system configuration is shown in figure 1.1. figure 1.1 typical dvd back-end system configuration video bitstream control dram mpeg-2 video decoder 27 mhz osc video encoder ST18-AU1 audio processor audio dac system layer controller audio bitstream control i 2 c i 2 s compressed system input bitstreams video output l/lt r/rt iec-958 (s/pdif) ac-3/mpeg
7/87 ST18-AU1 2 pin descriptions the following tables detail the ST18-AU1 pin set. there is one table for each group of pins. the tables detail the pin name, type and a short description of the pin function. signal names have a bar above if they are active low, otherwise they are active high. table 2.1 direct i bus extension (35 pins) pin name type description ide0-15 i/o instruction data extension bus. iae0-15 o instruction address extension bus. irde o i-extension bus read strobe. active low. iwre o i-extension bus write strobe. active low. ibse o i-extension bus strobe. active low. asserted at the beginning of i-bus read/ write cycle.
8/87 ST18-AU1 table 2.2 direct x bus extension / bus extension through bus switch unit (39 pins) table 2.3 general purpose parallel port (8 pins) pin name type description ed0-15 i/o bus switch unit (bsu) x/y/i data extension bus. ea0-15 o bsu x/y/i address extension bus. eird o bsu i-extension bus read strobe eird output. eiwr o bsu i-extension bus write strobe eiwr output. xbse o x_extension bus data strobe (bsu not used). eyrd o bsu y-extension bus read strobe eyrd output. eywr o bsu y-extension bus write strobe eywr output. xrde_exrd o multiplexed output. in direct x-bus extension mode (bsu not used) : x-extension bus read strobe (xrde). active low when reading from exter- nal x-memory. in x extension through bsu mode : bsu x-extension bus read strobe (exrd). active low when reading from external memory (when bit i/m of xer register is `1': intel mode). bsu extension bus data strobe (eds). active low when reading from or writ- ing to external memory (when bit i/m of xer register is `0' motorola mode). xwre_exwr o multiplexed output. in direct x-bus extension mode (bsu not used) : x-extension bus write strobe (xwre). active low when writing to external x-memory. in x extension through bsu mode : bsu x-extension bus write strobe (exwr). active low when writing to ex- ternal memory (when bit i/m of xer register is `1': intel mode). extension bus read /write signal (erd_wr). low during write cycle, other- wise high (when bit i/m of xer register is `0': motorola mode). pin name type description p0-7 i/o parallel port i/o. each pin can be programmed as input or output. on reset, all pins are inputs.
9/87 ST18-AU1 table 2.4 clocks (13 pins) table 2.5 i 2 c host interface (3 pins) pin name type description extal0 i oscillator0 input. dsp pll. xtal0 o oscillator0 output. nominal oscillator frequency is 27 mhz. extal1 i oscillator1 input. audio pll xtal1 o oscillator1 output. nominal oscillator frequency is 27 mhz. clk0 i direct clock input for d950 core. clk0_mode i clock0 mode select input. when low, select output of dsp pll for dsp clock in when high, select clk0 (bypass dsp pll) for dsp clock in clk1 i direct audio clock input. clk1_mode i clock1 mode select input. when low, select output of audio pll for audio clock when high, select clk1 (bypass audio pll) for dsp clock in pll_mode i pll mode select input when low, select oscillator 1 for audio pll when high, select oscillator 0 for audio pll clkout o output clock (at input clock/2 frequency). incycle o instruction cycle. asserted high for 1 clkout cycle at the beginning of instruction cycle. sclk i/o external audio clock/audio clock prescaler output mclk_mode i sclk mode select input when low, sclk = output (internal audio master clock from clock prescaler) when high, sclk = input (external audio master clock) pin name type description hda i/o i 2 c data input/output (open drain output). hcl /o i 2 c clock input/output (open drain output). hsas i slave address select
10/87 ST18-AU1 table 2.6 data input 0 (4 pins) table 2.7 data input 1 (3 pins) table 2.8 pcm output (5 pins) table 2.9 iec-958 transmitter (spdif) output (1 pin) table 2.10 interrupt controller interface (1 pin) pin name type description din0 i serial data input clkdin0 i/o data input clock input in slave mode, output in master mode. wsdin0 i/o data input word select input in slave mode, output in master mode. dreq0 o request for data input. active low. pin name type description din1 i serial data input clkdin1 i data input clock input in slave mode, output in master mode. wsdin1 o data input word select input in slave mode, output in master mode. pin name type description pcm_out0 o pcm data output 0 pcm_out1 o pcm data output 1 pcm_out2 o pcm data output 2 sclkpcm o pcm output clock (common) wspcm o pcm output word select (common) pin name type description spdifout o s/pdif signal pin name type description irq i interrupt request. active low. maskable, programmable as falling edge or low level triggered (default is level triggered).
11/87 ST18-AU1 table 2.11 d950-core control (3 pins) table 2.12 emulation unit (4 pins) table 2.13 jtag ieee 1149.1 test access port(5 pins) pin name type description reset i reset input. active low. initializes the 950-core to the reset state. lp i low power input. active low. mode_reset i mode selection for reset. when low, forces reset address to 0x0000. when high, forces reset address to 0xfc00. pin name type description erq i emulator halt request. active low. halts program execution and enters emulation mode. idle o output flag asserted high when the processor is halted due to an emulation halt request or a valid breakpoint condition.asserted low when the proces- sor is not halted or during execution of an instruction under control of the emulator. haltack o halt acknowledge. active high. asserted high when the processor is halted from an emulator halt request or when a valid breakpoint condition is met. snap o snapshot. active high. asserted high when executing an instruction if snapshot mode is enabled. pin name type description tdi i test data input. tck i test clock. tms i test mode select. tdo o test data output. trst i test logic reset (also used for emulator module). active low.
12/87 ST18-AU1 3 functional overview a functional block diagram of the ST18-AU1 is shown in figure 3.1. the modules that comprise the ST18-AU1 are outlined below and more detailed information is given in the following chapters of this datasheet. the interconnection of these blocks and all external interfaces are shown in the block diagram in figure 3.2. figure 3.1 functional block diagram timer host interface serial packet demux interface linear pcm mpeg2 decoder dolby ac-3 decoder processor down mix (surround) (or karaoke modes) serial s/pdif formatter output system manager delay clock inputs commands status data input 2 to 6 channel pcm output s/pdif output (ac-3/mpeg or 2 ch pcm)
13/87 ST18-AU1 figure 3.2 ST18-AU1 block diagram host interface the i 2 c serial bus interface operated in slave mode enables connection to an external host processor. it receives operating commands, and returns host requested bitstream information and internal status. interrupt controller clocks and timers host interface 2 tap 16k program memory 16k x-data 8k y-data memory iec-958 dma controller d950 dsp core ST18-AU1 p0-7 reset vcc gnd clocks hcl hda hsas (i 2 c host interface) din wsdin clkdin dreq spdifout (ac-3/mpeg or pcm) ieee 1149.1 jtag interface pcm_out sclkpcm wspcm i-bus x-bus y-bus it 9 bus switch unit direct x / bus input serial interfaces memory irq (s/pdif) output 3 output serial interfaces switch (39 pins) (13 pins) mode_reset lp direct i bus (35 pins)
14/87 ST18-AU1 input serial interface the ST18-AU1 has two input serial interfaces. the interfaces are multi-format serial interfaces for inputting audio bitstreams. supported formats include delayed (i 2 s)/non-delayed, left/right justified, 16/18/20/24-bit word, polarity options in l/r clock and input clock, and master/slave mode. they provide the serial to parallel conversion and transfer the input data to the input buffer for further processing. output serial interface the ST18-AU1 has three output serial interfaces. the output serial interfaces organize the pcm audio output into the required i 2 s serial format and generate all the dac control signals. iec-958 transmitter the iec-958 transmitter accepts either the ac-3/mpeg bitstream or the decoded audio output pcm data, and formats the input in accordance with the iec-958 (s/pdif) specification for output. interrupt controller (itc) the interrupt controller (itc) manages the interrupts from the clocks and timers unit, the host interface, and the external interrupt for the dsp core. the interrupt can be activated and programmed as edge or level triggered. dma controller (dmac) the dma controller (dmac) controls data transfer between data input/output and internal data buffers. d950 dsp core the d950-core is a general purpose programmable 16-bit fixed point digital signal processor core. the main blocks of the d950-core include an arithmetic data calculation unit, a program control unit and an address calculation unit, able to manage up to 64k (program) and 128k (data) x 16-bit memory spaces. the dsp core processes all host commands, performs input bitstream parsing, decompression, sample down-mixing and/or subsampling, as well as input and output control. memory there is 8 kword y-data memory on y space, 16 kword x-data memory on x space and 16 kword instruction memory on i space. memory can be extended off-chip in one of three ways: ? direct i-bus extension. ? direct x-bus extension. ? i, x and y -bus extension through the bus switch unit.
15/87 ST18-AU1 bus switch unit the bus switch unit (bsu) is a bi-directional switcher. it switches the 3 internal buses (i, x and y) to the external (e) bus. clocks and timers unit the clocks and timers unit provides all the necessary clocks and timer controls for dsp processing, and all input/output operations. in addition, a 90 khz system time clock (stc) is provided to assist audio/video synchronization in systems which include a video decoder. emulation unit and jtag ieee 1149.1 test access port the emulation unit (emu) performs functions dedicated to emulation and test through the external ieee 1149.1 jtag interface.
16/87 ST18-AU1 4 host interface the host interface is a fast i 2 c serial bus interface operated in slave mode. it provides connection to an external host processor. it receives operating commands, and returns host requested bitstream information and internal status. 4.1 host interface registers hser: host serial shift register this 16-bit shift register is used for serial data input and output. data is shifted msb first. it is not visible from the d950. hdr: host data register this register is used for transfers between the hser register and the d950. figure 4.1 host interface data exchange, receive mode msb654321lsb hcl hda ack byte 0 msb654321lsb byte 1 ..... yd hdr (16-bit words) hda byte 0 byte 1 msb lsb 16-bit 16-bit msb lsb yd 8-bit (msb) 8-bit (lsb) `0' byte 0 8-bit (msb) (lsb) hdr (8-bit words) hda hser hser
17/87 ST18-AU1 figure 4.2 host interface data exchange, send mode hcr: host control register all bits are cleared on reset. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - ber- rien ack- fien stopi- en - htien - - - - - ack- off ws hen bit function hen host interface enable 0 host interface disabled 1 host interface enabled ws word size 0 8-bit word 1 16-bit word ackoff acknowledge generation disable 0 acknowledge enabled 1 acknowledge disabled msb654321lsb hcl hda ack byte 0 msb654321lsb byte 1 ..... yd hdr (16-bit words) hda byte 0 byte 1 msb lsb 16-bit 16-bit msb lsb yd 8-bit (msb) byte 0 8-bit (msb) (lsb) hdr (8-bit words) hda hser hser
18/87 ST18-AU1 hsr: host status register all bits are reset when the register is read. the register can only be read by the d950. htien transfer interrupt enable 0 transfer interrupt disabled 1 transfer interrupt enabled stopien stop interrupt enable 0 stop interrupt disabled 1 stop interrupt enabled ackfien acknowledge fail interrupt 0 acknowledge fail interrupt disabled 1 acknowledge fail interrupt enabled berrien bus error interrupt 0 bus error interrupt disabled 1 bus error interrupt enabled - reserved, read as 0. 15141312 11 10 9 8 765432 1 0 - - - berr ack- fail stop hdrr rq hdrw rq ------ dat- adir busy bit function busy set when valid slave address detected, until stop event or restart event with invalid slave address. datadir data direction (valid when busy bit is set). 0 receive data from host 1' send data to host hdrwrq hdr write request. set when data is required by the host. data needs to be written into the hdr register, this is reset when the hsr register is read. hdrrrq host read request. set when data has been sent by the host. data needs to be read from the hdr register, this is reset when the hsr register is read. stop stop. set when a stop condition is detected. ackfail acknowledge fail. set when the host does not generate an acknowledge after one data byte has been sent. berr bus error. set when a misplaced start or stop condition is detected during transmission. - reserved, read as 0.
19/87 ST18-AU1 hsar: host slave address register (default value for slave address on reset: hsas (7...2) = 101000). 4.2 list of host commands a list of host commands is given below. 15 14 13 12 11 10 9 8 76543210 hsa7 hsa6 hsa5 hsa4 hsa3 hsa2 hsa1 hsa0 -------- bit function hsa0 data direction (read only, written from hser when slave address is send by the host. hsa1 slave address bit 1 (read only, value of pin hsas) hsa2 slave address bit 2 hsa3 slave address bit 3 hsa4 slave address bit 4 hsa5 slave address bit 5 hsa6 slave address bit 6 hsa7 slave address bit 7 - reserved, read as 0.
20/87 ST18-AU1 table 4.1 write commands mnemonic opcode size (bits) command description and parameter values hostinputmode 00 8 input mode (type of bitstream). ac3 (default) 00 mpeg -1 01 mpeg-2 02 mpeg-2 with extension 03 pcm by pass 04 linear pcm 05 hostinputstrmformat 01 8 input stream format es (default) 00 dvd/pes 01 hostopmode 02 8 operating mode idle (no decoding) (default) 00 start (starts selected decoder) 01 stop and flush (stops decoder and flush buffers) 02 reset 03 selftest 04 hostmute 03 8 mute off (default) 00 on 01 hostaudistrmidsel 04 8 audio stream id select id = 0 (default) to 7 (e.g. language selection)00 - 07 hostoutputchanconf 05 8 output channel configuration. 2/0 lt/rt, dolby surround compatible x0 1/0 c x1 2/0 l/r (default) x2 3/0 lcr x3 2/1 lrl x4 3/1 lcrl x5 2/2 lrlr x6 3/2 lcrlr x7 karaoke capable no vocal 0x karaoke capable vocal 1 1x karaoke capable vocal 2 2x karaoke capable vocal 1& 2 (default karaoke) 3x where x = do not care hostdualmonorepromode 06 8 dual mono reproduction mode stereo (default) 00 left mono 01 right mono 02 mixed mono 03
21/87 ST18-AU1 hostdynrngecompmode 07 8 dynamic range compression mode line-out mode 00 custom mode, analog dialnorm 01 custom mode, digital dialnorm (default) 02 rf demod mode 03 hostdynrngecutscalefac 08 16 dynamic range compression cut scale factor 0 to 0x7fff (at `0' the compression is minimum, at 0x7fff the compression is maximum). (default: 0x 7fff) hostdynrngebstscalefac 09 16 dynamic range compression boost scale factor 0 to 7fff (at `0' the boost is minimum, at 0x7fff the boost is maximum). (default: 0x7fff) hostpcmscalefac 0a 16 pcm scale factor 0 to 7fff (default) hostoutlfeon 0b 8 output lfe present off (default) 00 on 01 hostspdifoutstrmformat 0c 8 spdif output stream format (the spdif output can send either the pcm decoded output, or the input encoded elementary stream) ac3/mpeg (default) 00 pcm 01 hostspdifoutputlatency 0d 16 spdif output latency delay between the decoder and the bitstream sent via the spdif output. the delay is expressed in multiples of 1/fs, where fs is the sample frequency. the delay is signed. 0xffff to 0x7ffff (default: 0) hostspdifsmptefrmrat- cod 0e 16 spdif smpte frame rate code not indicated 00 24/1001 01 24 02 25 03 30/1001 (default) 04 30 05 50 06 60/1001 07 60 08 table 4.1 write commands mnemonic opcode size (bits) command description and parameter values
22/87 ST18-AU1 hostlpcmmixalpha0-7 hostlpcmmixbeta0-7 0f-16 17-1e 16 linear pcm downmixing coefficients in lpcm mode: alphai is the coefficient to downmix the channel i into the left channel. betai is the downmixing coefficient for channel i into the right channel. in ac-3 karaoke mode: the alpha0 to alpha5 are used to downmix respectively the left, melody, right, vocal1, vocal2 channels. beta0 to beta5 is respective- ly used to downmix into the right channel. alpha0 to alpha7, beta0 to beta7. hosterrorconcealmod 1f 8 error concealment mode mute (default) 00 disabled 01 skip 02 hostlowpower 20 8 low power stand-by mode off (default) 00 on 01 hostserialinputctrl 21 serial input control defines the input format. default: i2s slave hostserialinoutdiv 22 serial input clock division in master mode define the clock rate of the input . ) hostserialoutputctrl 23 serial output control defines the output format. default: i2s master hostserialoutputdiv 24 16 serial output clock division in master mode define the clock rate of the output. default: set for 44.1 hz hostaudioclocksel 25 audio clock selection all clocks derived from the 27mhz (default) 11 hostsamplfreq 26 16 audio sample frequency (hz) 3200 10 44100 (default) 00 48000 01 hostpcmnbbits 27 16 number of bits per sample 16 (default) 16 18 18 20 20 writestc 80 32 system time clock table 4.1 write commands mnemonic opcode size (bits) command description and parameter values
23/87 ST18-AU1 table 4.2 read commands mnemonic opcode size (bits) command description and parameter value hostversion 40 16 version number hosti2cstatus 41 8 i2cstatus no error 00 error 01 hostinputstatus 42 8 inputstatus no error 00 overflow 01 underflow 02 hostoutputstatus 43 8 outputstatus no error 00 underflow 01 overflow 02 error decoder 04 hostspdifstatus 44 8 spdif status no error 00 error 01 hostopmode 45 8 outputmode (refer to output channel configuration) hostauddecoderrorstatus 46 16 audio decoder error status no error 0 sync word 1 sample frequency 2 frame size 3 number of channels 4 decoder errors 5 f crc 10 hostinputsamplfreq 47 8 input sampling frequency sampling frequency specified by the bitstream. for ac-3 fscod is returned. hostinputdatrate 48 8 input data rate data rate specified by the bitstream. for ac-3 frmsizecod is returned. hostinputmultichanmode 49 8 inputmultichannelmode for ac-3 acmod is returned. hostkaraokcapbitstrm 4a 8 karaoke bitstream non karaoke 00 karaoke 01
24/87 ST18-AU1 hostlfepresent 4b 8 lfe present lfe not present 00 lfe present 01 hodtcopyprotect 4c 8 copy protected not protected 00 protected 01 hostopmodeout 4d 8 operating mode idle 00 synchronising 01 decoding 02 hostinputbitstrmstatus 4e 8 input bitstream status idle 00 searching for pes sync word 01 searching for audio frame sync word 04 stc 81 32 system time clock pts 82 32 presentation time stamp table 4.2 read commands mnemonic opcode size (bits) command description and parameter value
25/87 ST18-AU1 5 input serial interface the ST18-AU1 has two input serial interfaces (din0 and din1). the interfaces are multi- format serial interfaces for inputting audio bitstreams. supported formats include delayed (i 2 s)/non-delayed, left/right justified, 16/18/20/24-bit word, polarity options in l/r clock and input clock, and master/slave mode. they provide the serial to parallel conversion and transfer the input data to the input buffer for further processing. data input interface 0 (din0) operates with an input fifo which regulates the input data flow transferred to the input buffer. data input interface 1 (din1) operates in a similar way to din0 but it does not have an associated input fifo. 5.1 input serial interface registers each input serial interface has the following set of registers. din0-1cr: data in control register on reset, all bits are cleared. 1514131211109876543210 -------- mas- ter justi- fied de- layed ws_p ol clk_ pol ws din- en bit function dinen input interface enable 0 input interface disabled 1' input interface enabled ws input word size bit1 bit 0 input word size 0 0 16 bit 0 1 18 bit 1 0 20 bit 1 1 24 bit clk_pol clock polarity 0 data and ws change on clk falling edge 1 data and ws change on clk rising edge ws_pol word size polarity 0 left data word = ws low, right data word = ws high 1 left data word = ws high, right data word = ws low delayed delay inserted before first bit of data following transition of ws. 0 first bit of data occurs on transition of ws 1 first bit of data occurs with 1 clk cycle delay relative to transition of ws (i 2 s compatible).
26/87 ST18-AU1 din0-1div: data in division register on reset, din0div value is set to 0. din1dr: data in output register this 16-bit register contains the serial interface input data and is read by the d950. justified if number of clk cycles between ws transitions is > n (= word size) 0 start justified: n bits read, starting from first bit: just after ws transition if delayed ='0' with 1 clk cycle delay after ws transition if delayed='1' 1 end justified, end bit beein last bit received: just before ws transition if delayed ='0' just after ws transition if delayed ='1' master master or slave operation 0 slave 1 master note: this bit must be defined before the input interface enable (dinen) bit is set. - reserved, read as 0. 1514131211109876543210 -------- dindiv bit function dindiv mclk_din divide factor 00000000' 1 00000001 2 ..... ...... 11111111 '510 ` f clkdin = fmclk_din /2(din0div) if din0div /= `00000 reserved, read as 0.
27/87 ST18-AU1 5.2 input fifo associated with input serial interface 0 (din0) is a 32 byte input fifo. it is used for temporary storage of incoming data during processing of packet headers or ac3/mpeg decoding. the input fifo provides the following: ? transfer of data to the input buffer on a word basis ? packet header processing when operating on pes ? detection of fifo overflow and fifo filled to a predefined level 5.2.1 input fifo registers fifocr: input fifo control register on reset, all bits are cleared. the fifo is cleared and the formatter is set to the `empty' state. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - clr_fo rm - din0_ie n - dreq_ sel fifo_level dma_ mod dreq _en - bit function dreq_en dreq enable 0 dreq= 0 1 dreq set according to fifo threshold/full level dma_mod dma mode 0 dma request always enabled 1 dma request enabled only when pdc not equal to 0 (pes processing) fifo_level fifo threshold level (msb=7, lsb=3). set fifo filling level for irq/dreq manage- ment. dreq_sel dreq signal settings (if dreq_en = 1) 0 dreq is asserted high when fifo threshold is reached 1 dreq is asserted high when fifo is full (if dreq_en=1) din0_ien din0 interrupt enable 0 interrupt disabled 1' interrupt enabled (when fifo_ths = 1) clr_form set formatter empty (active only at write time of fifocr) - reserved, read as 0.
28/87 ST18-AU1 fifosr: input fifo status register fifo_full and fifo_thr are cleared on reset. fifo_out: fifo output data register form_out: formatter output data register pdcr: packet data count register cleared on reset. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - form_e mpty pdc_n ull fifo_t hr fifo_ empty fifo_f ull -------- bit function fifo_full fifo full: set and reset by hardware fifo_empty fifo empty: set and reset by hardware fifo_thr fifo threshold: set and reset by hardware pdc_null set when pdc = 0, otherwise reset form_empty set when formatter empty, otherwise reset - reserved, read as 0. 1514131211109876543210 data -------- bit function data data (msb=15, lsb=8) - reserved, read as 0. 1514131211109876543210 datah datal bit function data l data least significant byte data h data most significant byte 1514131211109876543210 ----- pdc bit function pdc packet data count value in bytes. maximum count value is 2047. - reserved, read as 0.
29/87 ST18-AU1 6 input and output buffers 6.1 input buffer the input buffer is single port memory mapped on the y space. taking into account the requirements for ac3 decoding and spdif transmitter, its size is 2048 words (16-bit). it is software defined and may be dynamically sized. buffer overflow detection is provided. the d950 reads the buffer using its circular addressing mode of operation. the dma controller cycles through the buffer for write word by word, using a cycle stealing mechanism: 3 d950 cycles are needed for each 16-bit word transfer. when the spdif transmitter is enabled, another dma channel is assigned to retrieving encoded samples. 6.2 output buffer the output buffer is single port memory mapped on the x space. for 2 channel and 6 channel pcm output, the size of the output buffer is software defined and can be dynamically sized. the d950 cycles through the buffer for write by using its circular addressing mode of operation. the dma controller cycles through the buffer for read of one sample at a time (2 or 3 words, depending on samples format), using a cycle stealing mechanism. in 2 channel output mode, one dma channel is used. in 6 channel output mode, three dma channels are used. the dma channel used must operate on alevelo mode. buffer underflow detection can be performed using on-chip dedicated resources. 6.2.1 input and output buffer registers bufcr: buffer control register all bits are cleared on reset. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ------ udf_out buf_ien ovf_inb uf_ien ----- udf_ mod ovf_in buf en_b uf bit function en_buf enable input/output buffer logic ovf_inbuf input buffer overflow 0 inbufovf= `0' 1 inbufovf=inbuf_full
30/87 ST18-AU1 bufsr: buffer status register all bits are cleared on reset. inbufrar:input buffer read address register this register is not initialized on reset. outbufwar: output buffer write address register this register is not initialized on reset. udf_mod output buffer underflow 0 outbufudf= `0' 1 outufudf=outbuf_empty ovf_inbuf_ien input buffer overflow interrupt enable 0 disable 1 enable udf_outbuf_ien output buffer underflow interrupt enable 0 disable 1 enable - reserved, read as 0. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ------ outbuf _empty inbuf_f ull -------- bit function inbuf_full input buffer full. set and reset by hardware. outbuf_empty output buffer empty. set and reset by hardware. - reserved, read as 0. 1514131211109876543210 radd bit function radd reference address for compare 1514131211109876543210 wadd bit function wadd reference address for compare.
31/87 ST18-AU1 7 output serial interface - pcm output the output serial interface organizes the pcm audio output into the required i 2 s serial format and generates all the dac control signals. the pcm output interface can be programmed to meet various data formats and modes of operation. the following parameters can be configured: word size, clock polarity, ws polarity, delayed/non-delayed, start/end justified. they are defined by the content of the control register pcmcr and are described below. 7.1 output serial interface registers pcmprx0-x2 (x = 0, 1, 2): data in parallel registers the 9 pcmpr registers are 16-bit pcm parallel registers used for temporary storage of output data. ? for 16-bit format, only the pcmprx0 and pcmprx1 registers are used respectively for channel 2 (right) and channel 1 (left). ? for formats of greater than 16-bits, the pcmprx2 registers are used for the lsb: ? channel 2 lsb on bits 7 to 0, left justified. ? channel 1 lsb on bits 15 to 8, left justified. figure 7.1 pcmpr register example for 18-bit data words t pcmpr00 bit15 bit0 ch2 17 ch2 2 17 16......... ..... ..2 ch1 ..... ch2 10 ch1 unused unused pcmpr01 pcmpr02 bit7 bit8 0 1 16......... ch1
32/87 ST18-AU1 pcmcr: data in control register all bits are cleared on reset. 1514131211109876543210 - - - mute _en play mute pcm _ord mode - justi- fied de- layed ws_p ol clk_ pol ws pc- men bit function pcmen pcm output enable 0 disable 1 enable ws output word size bit 1 bit 0 word size 0 0 16 bit 0 1 18 bit 1 0 20 bit 1 1 24 bit clk_pol clock pol 0 data and ws change on sclkpcm falling edge 1 data and ws change on sclkpcm rising edge ws_pol word size pol 0 left data word = ws low, right data word = ws high 1 left data word = ws high, right data word = ws low delayed delayed 0 first bit of data occurs on transition of ws 1 first bit of data occurs with 1 sclkpcm cycle delay relative to transition of ws. (i 2 s compatible). note: valid only for start justified mode, see bit 6. justified if number of sclkpcm cycles between ws transitions is > n (=word size) 0 start justified: n bits read, starting from first bit: just after ws transition if delayed ='0' with 1 clk cycle delay after ws transition if delayed ='1' 1 end justified, end bit in last bit received: just before ws transition if delayed ='0' just after ws transition if delayed ='1' mode mode 0 2 channels 1 6 channels pcm_ord in 16-bit word-size, 0 msb sent first 1 lsb sent first
33/87 ST18-AU1 pcmdiv on reset, the pcmdiv value is set to 0. if the spdif transmitter is used: ? if output word size is greater than 16-bit, pcmdiv must be set to at least 1 (divide by 2) for correct generation of spdifclk at twice the frequency of sclkpcm. ? if output word size is 16-bit, pcmdiv must be set to at least 2 (divide by 4). mute play mute 0 0 no dma req. serial out = 0 sclk, ws not running 0 1 no dma req. serial out = 0 sclk, ws running 1 0 dma req. serial out = 'data' sclk, ws running 1 1 dma req. serial out = 0 sclk, ws running play mute_en mute enable 0 disable mute input 1 enable mute input bit mute is set by detection of falling edge on mute input it is cleared by writing `0' to it. - reserved, read as 0. 1514131211109876543210 -------- pcmdiv bit function pcmdiv pcmclk divide factor 00000000 1 00000001 2 ... ... 11111111 510 f pcmclk = fmclk_pcm /2(pcmdiv) if pcmdiv /= `00000 - reserved, read as 0.
34/87 ST18-AU1 8 interrupt controller the interrupt controller (itc) manages the interrupts from the clocks and timers unit, the host interface, and the external interrupt for the dsp core. the interrupt controller also manages input/output buffer overflow/underflow interrupts. the interrupt controller has the following features: ? 8 interrupt sources ? interrupts can be individually enabled by software ? priority level between different sources can be set by software ? interrupt can be activated and programmed as edge or level triggered. the interrupt controller itrq inputs are connected to one external interrupt request (irq pin) and to internal peripheral requests, as detailed in the table below. table 8.1 interrupt assignments interrupt assignment itrq0 host interface itrq1 input fifo itrq2 input buffer itrq3 output buffer itrq4 clock timer irq itrq5 spdif timer irq itrq6 dma controller itrq7 connected to the external irq pin
35/87 ST18-AU1 figure 8.1 d950core interrupt controller 8.1 interrupt controller registers the interrupt controller interface is controlled by status and control registers mapped into the y-memory space. status registers are not write-protected. ivo0-7: interrupt vector0-7 address registers the ivo0-7 registers contain the first address of the interrupt routine and are associated with the respective interrupt input itrq, see table 8.1. the register content of the interrupt under service is provided on the yd bus during the cycle following the itack falling edge. (address = 0020-0027, no reset value, read/write) icr: interrupt control register the icr register displays the current priority level and up to four stacked priority levels. (address = 0028, reset = 000bh, read/write)) 15 14 13 12 11 10 9876543210 ivi15 ivi14 ivi13 ivi12 ivi11 ivi10 ivi9 ivi8 ivi7 ivi6 ivi5 ivi4 ivi3 ivi2 ivi1 ivi0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 spl4 (2:0) spl3 (2:0) spl2 (2:0) spl1 (2:0) es cpl (2:0) yd ya 16 16 d950core interrupt controller peripheral itrq1 it itack eoi ywr reset clk incycle it itack ywr yrd yrd eoi itrq0 itrq2 itrq3 itrq4 itrq5 itrq6 itrq7 as-dsp vr02020c
36/87 ST18-AU1 the current priority levels available are shown below. one interrupt request is acknowledged whenever its priority level (coded in the ipr register) is higher than the current priority level. in this case, the current priority level becomes the interrupt priority level and the previous current priority level is pushed onto the stack and displayed as stack priority level (spl)1. the process is repeated over a range of four interrupt requests and the four previous current stack priority levels are displayed on spl1, spl2, spl3 and spl4. if less than four interrupts are pushed onto the stack, the unused spl words are set to `000'. at the end of the interrupt routine, the priority levels are popped from the stack. the empty stack (es) flag is used to indicate whether the stack is used or not. the isp word of the isp register indicates the depth of the stack (see below). bit function cpl current priority level (-1, 0, 1, 2 or 3) (default is 011) es empty stack flag 0: stack is used 1: stack is not used (default) spl1 3-bit 1st stacked priority level spl2 3-bit 2nd stacked priority level spl3 3-bit 3rd stacked priority level spl4 3-bit 4th stacked priority level priority level coding acceptable it level priority - 1 111 0,1,2,3 0 000 1,2,3 1 001 2,3 2 010 3 3 011 reserved 100 - 110
37/87 ST18-AU1 figure 8.2 icr and ispr operation imr: interrupt mask/sensitivity register (address = 0029, reset = 5555h, read/write)) each interrupt input itrq0-7 can be masked individually when the corresponding im0-7 bit is set. in this case any activity on the itrq0-7 pin is ignored. all im bits are set during dsp reset. itrq0-7 is active either on a low level when is0-7 is low (by default on reset) or on a falling edge when is0-7 is high. when itrq0-7 is active on a low level, it must stay low until the itack falling edge is sampled. note, edge sensitive mode of operation must be set for all internal interrupt sources. 1514131211109876543210 is7 im7 is6 im6 is5 im5 is4 im4 is3 im3 is2 im2 is1 im1 is0 im0 bit function im interrupt mask 0: interrupt is not masked 1: interrupt is masked (default) is sensitivity 0: itrq is active on a low level (default) 1: itrq is active on a falling edge spl4 spl3 spl2 spl1 es cpl interrupt level 2 program program it2 program it3 it2 it3 interrupt level 3 xxxx1 -1 spl4 spl3 spl2 spl1 es cpl xxx-10 2 spl4 spl3 spl2 spl1 es cpl xx-120 3 01 2 isp isp isp icr ispr vr02020d
38/87 ST18-AU1 ipr: interrupt priority register (address = 002a, reset = 0000h, read/write) the ipr register contains the priority level of each itrq0-7 interrupt input. ip0-7 priority level is coded using two bits. the different values of ip are 0, 1, 2, 3 (0 lowest priority, 3 highest priority). when two itrq with the same priority level are requesting during the same cycle, the first acknowledged interrupt is the one corresponding to the lowest number (for example, itrq0 acknowledged prior to itrq3). ispr: interrupt stack pointer register (address = 002b, reset = 0000h, read/write) note: '-' is reserved (read: 0, write: don't care) ispr contains the number of stacked priority levels. if the ispr value is directly written, the spli/cpl values are modified. so the icr register content is no longer significant but the interrupt routine procedure is not affected. after reset, ispr default value is 0 isr: interrupt status register (address = 002c, reset = 0000h, read/write) note: ` -' is reserved (read: 0, write: don't care) 1514131211109876543210 ip7(1:0) ip6(1:0) ip5(1:0) ip4(1:0) ip3(1:0) ip2(1:0) ip1(1:0) ip0(1:0) bit function ip interrupt priority level (0, 1, 2 or 3) (default is 0) 1514131211109876543210 ------------- isp(2:0) bit function ispr number of stacked priority levels (0, 1, 2 or 3) 1514131211109876543210 - - - - - - - ipe7 ipe6 ipe5 ipe4 ipe3 ipe2 ipe1 ipe0 bit function ipe interrupt pending bit 0: reset when interrupt request is acknowledged (default) 1: set when interrupt request is recorded
39/87 ST18-AU1 an interrupt pending (ipe) bit is associated with each interrupt input. ipe is set when the interrupt request is recorded and is reset when the interrupt request is acknowledged (itack falling edge). when the user does not want to acknowledge any of the pending interrupt requests, the ipe flag of the ccr register must first be reset and then the isr register set to a0000o. when only some pending interrupt requests need to be acknowledged, the ipe bits of the other interrupt inputs must be reset. when the ipe bit is set by a direct register write an interrupt request will be generated irrespective of the state of the itrq pin. when the mask (im) bit is set, the corresponding ipe bit is reset.
40/87 ST18-AU1 9 dma controller the dma controller manages data transfer between memories and external peripherals and has the following features: ? four independent dma channels ? transfers on x / y / i spaces (simultaneous transfers on x and y spaces) ? cycle stealing operation: ? 3 cycles for a single data transfer (+1 cycle for transfers on i space) ? (n+2) cycles for an n-data block transfer (+1 cycle for transfers on i space) ? each channel has: ? 1 signal: interrupt request (itr) ? 4x16 bit registers for block transfer facilities ? fixed priority between the four channels (highest for channel 0, lowest for channel 3) 9.1 dma operation the four channels of d950 dmac are used for: ? dma3: transfer data from input fifo to input buffer (y space). as single words are transferred, it must be programmed edge sensitive. ? transfer data from output buffer to pcm output (x space). ? dma0 in 2-channel output mode ? dma0, dma1 and dma2 in 6-channel output mode they must be programmed level sensitive. ? dma1: transfer data from input buffer or output buffer to spdif interface. this channel will be programmed for transfer with x or y memory according to the mode of operation of the spdif transmitter. it must be programmed level sensitive. (not compatible with 6-channel output mode.) ? dma2: transfer data from data input1 to y memory. as single words are transferred, it must be programmed edge sensitive. (not compatible with 6-channel output mode.)
41/87 ST18-AU1 9.2 dma registers 9.2.1 address registers two 16-bit registers (unsigned) are dedicated per channel for transfer address: ? dia0-3: initial address. this register contains the initial address of the selected address bus (see dbc-bit of dgc register). ? dca0-3: current address. this register contains the value to be transferred to the selected address bus (see dbc-bit of dgc register) during the next transfer. the different dca values are: note: see daic register for dai and dla definitions. 9.2.2 counting registers two 16-bit registers (unsigned) per channel are dedicated for transfer count. for a transfer of an n data block, dic and dcc registers have to be loaded with n-1 . when dcc content is 0 (valid transfer count), it is loaded with dic content for the next transfer. ? dic0-3: initial count. this register contains the total number of transfers of the entire block. ? dcc0-3: current count. this register contains the remaining number of transfers required to fill the entire block. it is decremented after each transfer. the dcc values are: reset dai dla dcc dca(n+1) 1xxx0 0 0 x x dca(n) 0 1 0 x dca(n) + 1 0 1 1 =0 dca(n) + 1 0 1 1 =1 dia reset dcc dca(n+1) 1x0 0 =0 dca(n) - 1 0=1dic
42/87 ST18-AU1 9.2.3 control registers three 16-bit control registers are dedicated to the dma controller interface. these are the general control register, the address interrupt control register and the mask sensitivity control register. they are detailed below. dgc: general control register three bits are dedicated for each dma channel (bits 0 to 2 to channel 0, bits 4 to 6 to channel 1, bits 8 to 10 to channel 2, bits 12 to 14 to channel 3). (address = 0040, reset = 0000h, read/write). daic: address/interrupt control register four bits are dedicated for each dma channel (bits 0 to 3 to channel 0, bits 4 to 7 to channel 1, bits 8 to 11 to channel 2, bits 12 to 15 to channel 3). (address = 0042, reset = 0000h, read/write) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - drw 3 dbc 1 dbc 0 - drw 2 dbc 1 dbc 0 - drw 1 dbc 1 dbc 0 - drw 0 dbc 1 dbc 0 bit function dbc1/dbc0 bus choice for data transfer 00: x-bus (default) 01: y-bus 10: i-bus 11: reserved drwi data transfer direction 0: write access (default) 1: read access 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dai3 dla3 dip3 die3 dai2 dla2 dip2 die2 dai1 dla1 dip1 die1 dai0 dla0 dip0 die0 bit function diei enable interrupt 0: interrupt request output associated to channel i is masked (default) 1: interrupt request output associated to channel i is not masked dipi interrupt pending 0: no pending interrupt on channel i (default) 1: pending interrupt on channel i (enabled if dip_ena input is high)
43/87 ST18-AU1 dms: mask sensitivity control register two bits are dedicated to each dma channel (bits 0 and 1 to channel 0, bits 4 and 5 to channel 1, bits 8 and 9 to channel 2, bits 12 and 13 to channel 3). (address = 0041, reset = x3333h, read/write) dlai: load address 0: dcai content incremented after each data transfer (default) 1: dcai content loaded with dia content if dcci value is 0, or dcai content incremented if dcci value is not equal to 0 daii address increment 0: dcai content unchanged (default) 1: dcai content modified according to dlai state 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - dse3 dmk3 - - dse2 dmk2 - - dse1 dmk1 - - dse0 dmk0 bit function dmki dma mask 0: dma channel not masked 1: dma channel masked (default) dsei dma sensitivity 0: low level 1: falling edge (default)
44/87 ST18-AU1 10 iec-958 transmitter the iec-958 transmitter accepts either the ac-3/mpeg bitstream or the decoded audio output pcm data, and formats the input in accordance with the iec-958 (s/pdif) specification for output via the spdifout pin. for further information refer to the iec-958 interface specification. 10.1 iec-958 transmitter registers chansta1: channel status register 1 note: write only register. chansta2: channel status register 2 note: write only register. bit bit of c function 0 0 0 consumer mode, fixed 1 1 digital data 0 audio data, muted or pcm 1 compressed audio data 2 2 copyright indication 0 digital copy prohibited 1 digital copy permitted 3-5 3-5 000 (reserved) 6-7 6-7 mode 0 00 (fixed) 8-14 8-14 category code 1001100 for dvd (ac3/mpeg) 15 genera- tion status 0 original/commercially pre-recorded 1 no indication/1st generation or higher bit bit of c function 0-7 16-23 00000000 (fixed) 8-11 24-27 0100 fs 48khz 0000 fs 44.1khz 1100 fs 32khz 12-13 28-29 00 clock precision fixed 14-15 30-191 all 0, fixed
45/87 ST18-AU1 spdifcr: spdif output control register note: write only register. all bits of the spdifcr register are cleared on reset. spdifpr0-2: 3x 16-bit spdif parallel registers the spdifpr0-2 registers are 16 bit spdif parallel registers used for intermediate storage of data. they are write only registers. bit name function 0 spdifen enable 0 disabled 1 enabled 1-2 ws word size bit 1 bit 0 word size 0 0 16 bit 0 1 18 bit 1 0 20 bit 1 1 24 bit 3 x/y select x/y for data read 0 y (input buffer) 1 x (output buffer) 4 v validity bit 0 valid 1 defective 5-15 reserved, written as 0.
46/87 ST18-AU1 11 memory 11.1 internal memory resource one 8 kword and two 16 kword single port memories are included on-chip: ? instruction memory on i space from address 0 to 16382 (16 k) ? x-data memory on x space from address 0 to 16382 (16 k) ? y-data memory on y space from address 256 to 8192 note: the first 256 addresses of the y space are reserved for the d950 memory-mapped registers and for on-chip memory mapped peripherals. memory can be extended off-chip in one of two ways: 1: directly for i and x memory spaces 2: through the bus switch unit for all three memory spaces the specific details on the operation of the bsu are described separately in chapter 12. figure 11.1 memory mapping x-memory y-memory i-memory 0000 8k ffff 64k 64k internal ram registers external internal ram external external all addresses are hexadecimal 3fff 00ff 64k 16k ffff 1fff ffff 0000 internal ram 3fff 16k external memory is accessed directly or through the bus switch
47/87 ST18-AU1 11.2 i-memory bus extension - direct and through bsu for direct bus extension for i-memory the internal program memory is used from address 0 to 16383 (16k). the bsu can be programmed to allow either direct extension or extension through the bsu for ia above 16383. note: initial reset should occur with mode_reset = 1, because internal program ram is not ini- tialized. 11.3 x-memory bus extension - direct and through bsu the internal program memory is used from address 0 to 16383 (16k). direct bus extension or bus extension through the bsu is controlled by setting the x-bus related bsu registers. 11.4 y-memory bus extension through bsu the internal program memory is used from address 256 to 8192. y-memory bus extension must be through the bsu. it is controlled by setting the y-bus related bsu registers.
48/87 ST18-AU1 12 bus switch unit the bus switch unit (bsu) is a bi-directional switcher. it switches the 3 internal buses (i, x and y) to the external (e) bus. 12.1 bsu control registers the bsu is programmable via six control registers mapped in the y-memory space. these define the type of memory used, internal to external boundary address crossing, exchange type (external direct or through the bsu) and software wait-states count. there are 2 registers per memory space, making it possible to define 2 sets of boundaries and wait state numbers. figure 12.1 default and user mapping examples the bsu control registers include a reference address on bits 4 to 9, where the internal/ external memory boundary value is stored (see figure 12.1), and software wait-states count on bits 0 to 3, allowing up to 16 wait-states. external addressing is recognized by comparing these address bits for each valid address from ia, xa and ya, to the reference address contained into the corresponding control register. if the address is greater or equal to the reference value, an external access proceeds. external inte rnal1 64k 63k 62k internal 0 defa ult mapping (reset) user mapping (can change by 1k step) value 1 value 0 value 1 value 0 exte rnal internal1 internal0 64k 0 0
49/87 ST18-AU1 xer0/1: x-memory space control registers after reset, xer0/1 default values are 0x83ef/0x83ff yer0/1: y-memory space control registers after reset, yer0/1 default values are 0x83ef/0x83ff ier0/1: instruction memory control registers after reset, ier0/1 default values are 0x83ef/0x83ff or 0xc3ef/0xc3ff (the en_i value depends on the idt_en input value). 1514131211109876543210 im en_x - - - - xa15 xa14 xa13 xa12 xa11 xa10 w3 w2 w1 w0 bit function w3:0 wait state count (1 to 16) for off-chip access (x-memory space) xa15:10 x-memory space map for boundary on-chip or off-chip en_x enable for x-space data exchanges im intel/motorola 0: motorola type for memories 1: intel type for memories (default) - reserved. r ead 0, write don't care. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 im en_y - - - - ya15 ya14 ya13 ya12 ya11 ya10 w3 w2 w1 w0 bit function w3:0 wait state count (1 to 16) for off-chip access (y-memory space) ya15:10 y-memory space map for boundary on-chip or off-chip en_y enable for y-space data exchanges im intel/motorola 0: motorola type for memories 1: intel type for memories (default) - reserved. r ead 0, write don't care. 1514131211109876543210 im en_i ---- ia15 ia14 ia13 ia12 ia11 ia10 w3 w2 w1 w0
50/87 ST18-AU1 bit function w3:0 wait state count (1 to 16) for off-chip access (i-memory space) ia15:10 i-memory space map for boundary on-chip or off-chip en_i enable for i-space data exchanges im intel/motorola 0: motorola type for memories 1: intel type for memories (default) - reserved. r ead 0, write don't care.
51/87 ST18-AU1 13 clocks and timers unit the clocks and timers unit provides all the necessary clocks and timer controls for dsp processing, and all input/output operations. in addition, a 90 khz system time clock (stc) is provided to assist audio/video synchronization in systems which include a video decoder. 13.1 operation 13.1.1 audio clock prescaler ? inputs ? audioclk: output of audio master clock pll ? mclk_mode: select internal or external audio system clock: (if bit clk_sel1 of register psctr='0') 0 = internal 1 = external ? outputs ? mclk_pcm to pcm output interface ? mclk_din to data input interface ? input/output ? sclk the programmable prescaler and clock dividers of data input and pcm output interfaces are used for the generation of data bit clocks. the prescaler divide range is 1 to 510. it is defined by the content of the psctr register. its output sclkint is a 50% duty cycle signal.
52/87 ST18-AU1 13.2 clocks and timers registers psctr register) stc: system time clock registers ? input = extal1 (27 mhz) ? output = stc a prescaler divides by 300 the master clock and generates the input clock at 90 khz for stc. the 90 khz clock is synchronized to the d950 instruction clock. stc is a 32-bit counter incremented at each 90 khz clock pulse. it can be initialized to any value and read by the d950. it is memory mapped as two registers, stcmtr and stcltr. stcmtr: 16-bit (msb) stcltr: 16 bit (lsb) note: when initializing the stc, the stcltr register must be written before the stclmtr. the effective loading of the stc occurs after stcmtr loading: when reading the stc, the stcltr register must be read first. at that time, the current value of the stc msb is stored in the stcmtr register, which can then be read. no interrupts are associated with the stc. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ------ clk_sel 2 clk_sel 1 sclkintdiv bit function sclkint- div sclkintdiv prescaler divide factor 00000000 1 00000001 2 ... ... 11111111 510 f sclkint = fpll2 /2(sclkintdiv) if sclkintdiv /= 00000000 clk_sel1 pcm output clock select: 0 hardware (mclk_mode pin) 1 software (according to bit 9) clk_sel2 pcm output clock select: 0 mclk_pcm= output of prescaler: sclk is system clock output 1 mclk_pcm= sclk: sclk is system clock input - reserved, read as 0.
53/87 ST18-AU1 blkclktr: block clock timer register ? input = fs (samples frequency) ? output = blkclk_irq the blkclktr register is a 16-bit decrementer. it can be initialized to any value by the d950. an interrupt request is generated when the blkclktr register is decremented to 0 and it is reset to its initial value. spdif timer register ? input = fs (samples frequency) ? output = spdif_irq the spdiftr register is a 16-bit decrementer. it can be initialized to any value by the d950. an interrupt request is generated when it is decremented to 0 and reset to its initial value.
54/87 ST18-AU1 figure 13.1 clocks and timers block diagram pcm_out timer (16-bit). spdif timer (16-bit). (27 mhz) psc (8-bit prescaler). fs div 300 stc (32 bit counter) extal0 audioclk mclk_mode sclk mux d950 y-bus blkclk_irq spdif_irq mclk_pcm mclk_din (sclkint) (in/out)
55/87 ST18-AU1 14 jtag ieee 1149.1 test access port the test access port (tap) conforms to ieee standard 1149.1. the tap consists of five pins: tms , tck , tdi , tdo and trst . tdo can be overdriven to the power rails, and tck can be stopped in either logic state. the instruction register is 8 bits long, with no parity, and the pattern a00000001o is loaded into the register during the capture-ir state. there are three defined public instructions, see table 14.1. all other instruction codes are reserved. table 14.1 instruction codes instruction code 1) 1) msb... lsb; lsb closest to tdo instruction selected register 04h idcode identification 08h emu d950 ioscan ffh bypass bypass
56/87 ST18-AU1 15 emulation unit the emulation unit (emu) performs functions dedicated to emulation and test through the external ieee 1149.1 jtag interface. refer to chapter 14 for details on the jtag test access port. the emulation and test operations are controlled by the jtag test access port (tap) and the emulator by means of dedicated control i/os. emulation mode can entered in one of two ways: ? asserting erq input pin low. ? meeting a valid breakpoint condition or executing an instruction in single step mode. the pc board emulator is able to display the processor status (memories and registers) and restore the context. the emulation resources (see figure 15.1) include: ? four breakpoint registers (bp0-3) which can be affected by program or data memory. ? breakpoint counter (bpc). ? program counter trace buffer (pcb) able to store the address of the 6 last executed instructions. ? three control registers for breakpoint condition programming (bc0-1 and ecs). ? control logic for instruction execution through the pc-board emulator control.
57/87 ST18-AU1 figure 15.1 emulation block diagram the emulation controller interface (see table 2.12 and table 2.13 on page 11) includes pins of different types: ? erq, idle and snap are used by the emulator tools. ? haltack indicates that the processor is halted in emulation mode. bp registers comparators xa / ya xd / yd ia control registers control logic pc trace erq, idle, snap rd/wr d950 tap ia
58/87 ST18-AU1 16 d950core the d950core is composed of three main units. ? data calculation unit (dcu) ? address calculation unit (acu) ? program control unit (pcu) for full details of the d950 dsp core refer to the d950core datasheet ( document number 42- 1709 ). these units are organized in an harvard architecture around three bidirectional 16-bit buses, two for data and one for instruction. each of these buses is dedicated to an uni- directional 16-bit address bus (xa/ya/ia). an 8-bit general purpose parallel port (p0-p7) can be configured (input or output). a test condition is attached to each bit to test external events. the d950core is controlled through interface pins related to interrupt, low-power mode, reset and miscellaneous functions. figure 16.1 d950core block diagram data calculation unit address calculation unit program control unit clkin data memory program memory vdd vss test & emulation po/p7 control 11 8 14 xd-bus yd-bus 6 16 16 16 16 3 16 16 output clocks xa-bus ya-bus id-bus ia-bus control
59/87 ST18-AU1 data buses (xd/yd and xa/ya) are provided externally. data memories (ram, rom) and peripherals registers are mapped in these address spaces. instruction bus (id/ia) gives access to program memory (ram, rom). each bus has its own control interface. table 16.1 data/instruction bus and corresponding address bus. depending on the calculation mode, the d950core dcu computes operands which can be considered as 16 or 32-bit, signed or unsigned. it includes a 16 x 16-bit parallel multiplier able to implement mac-based functions in one cycle per mac. a 40-bit arithmetic and logic unit, including an 8-bit extension for arithmetic operations, implements a wide range of arithmetic and logic functions. a 40-bit barrel shifter unit and a bit manipulation unit are included. the tables below illustrate the different types of word length and word format available for manipulation. table 16.2 summary of possible word lengths and formats data/instruction bus corresponding address bus xd bidirectional 16-bit xa unidirectional 16-bit yd bidirectional 16-bit ya unidirectional 16-bit id bidirectional 16-bit ia unidirectional 16-bit 0 1-bit word 7 0 8-bit word 15 0 16-bit word signed / unsigned 31 16 15 0 32-bit word signed / unsigned 39 32 31 16 15 0 40-bit word signed / unsigned format minimum maximum fractional signed - 1 + 0.999969481 unsigned 0 + 0.99996948 integer signed - 32768 + 32767 unsigned 0 + 65535
60/87 ST18-AU1 16.1 d950core registers pcdr the port control direction register defines the data direction of each port pin. after reset, pcdr default value is 0 (port pins are configured as inputs) pcsr the port control sensitivity register defines sensitivity of each port pin. after reset, pcsr default value is 0 (port pins are configured as level-sensitive). register function bx modulo base address for x-memory space mx modulo maximum address for x-memory space by modulo base address for y-memory space my modulo maximum address for y-memory space por port output register - 8lsb are significant, 8msb are undefined when reading pir port input register pcdr port control direction register pcsr port control sensitivity register ppr program page register 1514131211109876543210 --------p7dp6dp5dp4dp3dp2dp1dp0d bit function pid port pin direction 0: input port pin (default) 1: output port pin bits 8 - 15 reserved (read: undefined, write: don't care) 1514131211109876543210 --------p7sp6sp5sp4sp3sp2sp1sp0s bit function pis port pin sensitivity 0: level sensitive (default) 1: edge sensitive bits 8 - 15 reserved (read: undefined, write: don't care)
61/87 ST18-AU1 17 y space memory mapping 17.1 memory map figure 17.1 ST18-AU1 memory mapping reserved ffff 2000 internal y ram 1fff 0100 reserved 00ff 00b5 clocks and timers 00b4 00b0 reserved 00af 00a6 s/pdif 00a5 00a0 reserved 009f 009d pcm output 009c 0090 reserved 008f 0084 input/output buffer 0083 0080 reserved 007f 007b serial input 1 007a 0078 serial input 0 0076 0070 reserved 006f 0064 host interface 0063 0060 reserved 005f 0056
62/87 ST18-AU1 17.2 clocks and timers registers bus switch unit 0055 0050 reserved 004f 004a pll 0049 0048 reserved 0047 0043 dma controller 0042 0030 reserved 002f 002d interrupt controller 002c 0020 reserved 001f 0019 emulator peripheral 001f 0010 d950 core 000f 0000 address (hex) register description 00b0 psctr prescaler 00b1 stcltr system time clock lsb 00b2 stcmtr system time clock msb 00b3 blkclktr block clock timer 00b4 spdiftr spdif timer
63/87 ST18-AU1 17.3 iec-958 transmitter (s/pdif output) registers 17.4 pcm registers 17.5 input/output buffer registers address (hex) register description 00a0 spdifcr spdif control 00a1 spdifpr0 spdif data0 00a2 spdifpr1 spdif data1 00a3 spdifpr2 spdif data2 00a4 chansta1 channel status word1 00a5 chansta2 channel status word2 address (hex) register description 0090 pcmcr pcm output control 0091 pcmpr00 pcm output data 00 0092 pcmpr01 pcm output data 01 0093 pcmpr02 pcm output data 02 0095 pcmpr10 pcm output data 10 0096 pcmpr11 pcm output data 11 0097 pcmpr12 pcm output data 12 0099 pcmpr20 pcm output data 20 009a pcmpr21 pcm output data 21 009b pcmpr22 pcm output data 22 009c pcmdiv pcm output clock divide factor address (hex) register description 0080 bufcr in/out buffer control 0081 bufsr in/out buffer status 0082 inbufrar input buffer read address 0083 outbufwar output buffer write address
64/87 ST18-AU1 17.6 serial input 1 registers 17.7 serial input 0 registers 17.8 host interface registers 17.9 bus switch unit registers address (hex) register description 0078 din1cr data in 1 control 0079 din1div data in 1 divide factor 007a din1dr data in 1 output address (hex) register description 0070 din0cr data in 0 control 0071 din0div data in 0 divide factor 0072 fifocr fifo control 0073 fifosr fifo status 0074 fifoout fifo output 0075 form formatter 0076 pdcr packet data count address (hex) register description 0060 hcr host interface control 0061 hsr host interface status 0062 hsar slave address 0063 hdr host data register address (hex) register description 0055 yer1 external y-bus control register 1 0054 xer1 external x-bus control register 1 0053 ier1 external i-bus control register 1 0052 yer0 external y-bus control register 0 0051 xer0 external x-bus control register 0 0050 ier0 external i-bus control register 0
65/87 ST18-AU1 17.10 pll registers 17.11 dma controller registers address (hex) register description 0048 d950_plldiv d950_pll divide factor 0049 audio_plldiv audio_pll divide factor address (hex) register description 0042 daic dma address / interrupt control 0041 dms dma mask sensitivity 0040 dgc dma general control 003f dcc3 dma channel 3 current count 003e dcc2 dma channel 2 current count 003d dcc1 dma channel 1 current count 003c dcc0 dma channel 0 current count 003b dic3 dma channel 3 initial count 003a dic2 dma channel 2 initial count 0039 dic1 dma channel 1 initial count 0038 dic0 dma channel 0 initial count 0037 dca3 dma channel 3 current address 0036 dca2 dma channel 2 current address 0035 dca1 dma channel 1 current address 0034 dca0 dma channel 0 current address 0033 dia3 dma channel 3 initial address 0032 dia2 dma channel 2 initial address 0031 dia1 dma channel 1initial address 0030 dia0 dma channel 0 initial address
66/87 ST18-AU1 17.12 interrupt controller registers 17.13 d950 core control registers 002c isr interrupt status register 002b ispr interrupt stack pointer register 002a ipr interrupt priority register 0029 imr interrupt mask/sensitivity register 0028 icr interrupt control register 0027 iv7 interrupt vector 7 address 0026 iv6 interrupt vector 6 address 0025 iv5 interrupt vector 5 address 0024 iv4 interrupt vector 4 address 0023 iv3 interrupt vector 3 address 0022 iv2 interrupt vector 2 address 0021 iv1 interrupt vector 1 address 0020 iv0 interrupt vector 0 address address (hex) register description 0007 pcsr port control sensitivity register 0006 pcdr port control direction register 0005 pir port input register 0004 por port output register 0003 my y-memory space modulo max address 0002 by y-memory space modulo base address 0001 mx x-memory space modulo max address 0000 bx x-memory space modulo base address
67/87 ST18-AU1 17.14 data and program memory mapping x memory mapping y memory mapping i memory mapping address (hex) name function 0000 to 3fff on chip x ram (16k words). address (hex) name function 007f to 1fff on chip y ram (7936 words). addresses 00 to ff (256 words) reserved for d950 and peripherals memory mapped registers. i address (hex) name function 0000 to 3fff on chip i ram (16k words)
68/87 ST18-AU1 18 electrical specifications in the following tables tbd indicates `to be defined'. 18.1 dc absolute maximum ratings table 18.1 dc absolute maximum ratings 18.2 dc electrical characteristics table 18.2 dc electrical characteristics notes 1: iload = 2ma symbol parameter value unit vdd power supply voltage - 0.5 / 4 v vin input voltage -0.5 / vdd+0.5 v ta operating temperature range 0 / +70 o c tstg storage temperature range -55 / +150 o c symbol parameter min typ max unit notes v dd supply voltage 2.7 3.3 3.6 v v il input low level -0.3 0.8 v v ih input high level 2.0 vdd+0.3v v i in input current 10 m a v ol output low level 0.4 v 1 v oh output high level 2.4 v 1 i dd operating current 180 ma 3
69/87 ST18-AU1 18.3 ac characteristics the following timings are based on simulations and may change when full characterisation is completed. figure 18.1 input waveforms timing reference points 1.5v 1.5v 90% 90% 10% 10% d f d r d r, d f 2.5ns 2.7v 0.3v
70/87 ST18-AU1 figure 18.2 output load circuit and waveform table 18.3 ac measurement conditions - input only or output only pins v dd v il v ih v ol v oh i ol i oh vddmin 0.3v 2.7v 1.5v 1.5v 1ma 1ma vddmax 0.3v 2.7v 1.5v 1.5v 1ma 1ma ~ vref iol = 1ma ioh = 1ma from output under test cl = 50pf vol voh 1.5v 1.5v timing reference points
71/87 ST18-AU1 figure 18.3 float load circuit and waveform ~ vref iol = 8ma ioh = 8ma from output under test cl = 50pf vol voh voh - 0.15v timing reference points vref vref + 0.1v vref - 0.1v vol - 0.15v for timing purposes a pin is no longer floating when a 100mv change from vref occurs, but begins to float when a 150mv change from the loaded voh/vol level occurs.
72/87 ST18-AU1 18.3.1 clocks electrical characteristics (1): clk0_mode=0 (bypass pll) (2): clk1_mode=0 (bypass pll),mclk_mode=0 (select internal generation from clk1) no divide option set. (3):clk1_mode=0 (bypass pll),mclk_mode=0 (select internal generation from clk1) prescaler divide by 2 no parameter min (ns) typ (ns) max (ns) t1 clkout rise time t2 clkout fall time t3 clkout high delay(1) 7.05 t4 clkout low delay(1) 6.95 t5 incycle high delay 0.55 t6 incycle low delay t0-0.7 t7 sclk out rise time t8 sclk out fall time t9 sclk out high delay(2) 6.25 t9 sclk out high delay(3) 7.10 t10 sclk out low delay(2) 6.75 t10 sclk out low delay(3) 7.70 clk1 sclk(out) t9 t10 t8 t7 clk0 clkout incycle t3 t5 t4 t6 t2 t1
73/87 ST18-AU1 18.3.2 e-bus (i direct extension) no parameter min (ns) typ (ns) max (ns) t11 ibse low delay 0.3 t12 ibse high delay t0-1.4 t13 irde low delay t0/2-1.05 t14 irde high delay 0.35 t15 iwre low delay t0/2+0.9 t16 iwre high delay 0 t17 iae valid delay 1.6 t18 iae hold time 1.1 t19 ide (in) setup time 5.45 t20 ide (in) holdtime -4.40 t21 ide (out) valid delay (hi to lo z) t0+3.80 t22 ide (out) valid delay (lo to hi z) -0.1 clkout incycle ibse irde iae ide(in) iwre ide(out) t17 t18 t11 t12 t13 t14 t15 t16 t19 t20 t21 t22
74/87 ST18-AU1 18.3.3 e-bus (x direct extension) no parameter min (ns) typ (ns) max (ns) t23 xbse low delay 0.25 t24 xbse high delay t0+0.3 t25 xrde_exrd low delay t0+2.5 t26 xrde_exrd high delay 0.65 t27 xwre_exwr low delay t0+2.6 t28 xwre_exwr high delay 0.35 t29 ea valid delay t0+3.95 t30 ea hold time 3.30 t31 ed (in) setup time 7.50 t32 ed (in) hold time -5.85 t33 ed (out) valid delay (hi to lo z) t0+3 t34 ed (out) valid delay (lo to hi z) 0.3 clkout incycle xbse xrde_exrd ea ed (in) xwre_exwr ed (out) t29 t30 t23 t24 t25 t26 t27 t28 t31 t32 t33 t34
75/87 ST18-AU1 18.3.4 e-bus (i bsu) no parameter min (ns) typ (ns) max (ns) t35 eird low delay 2.55 t36 eird high delay 1.4 t37 eiwr low delay 2.15 t38 eiwr high delay 1.7 t39 ea valid delay t0+4.15 t40 ea hold time t0+3.90 t41 ed (in) setup time 8.25 t42 ed (in) hold time -6.55 t43 ed (out) valid delay (hi to lo z) 2 t44 ed (out) valid delay (lo to hi z) 1.95 clkout incycle eird ea ed (in) eiwr ed (out) t39 t40 t35 t36 t37 t38 t41 t42 t43 t44
76/87 ST18-AU1 18.3.5 e-bus (x bsu) no parameter min (ns) typ (ns) max (ns) t45 xrde_exrd low delay 3.65 t46 xrde_exrd high delay 2 t47 xwre_exwr low delay 3.15 t48 xwre_exwr high delay 1.95 t49 ea valid delay t0+4.65 t50 ea hold time t0+4.40 t51 ed (in) setup time 8.35 t52 ed (in) hold time -7.15 t53 ed (out) valid delay (hi to lo z) 4.85 t54 ed (out) valid delay (lo to hi z) 1.55 clkout incycle xrde_exrd ea ed (in) xwre_exwr ed (out) t49 t50 t45 t46 t47 t48 t51 t52 t53 t54
77/87 ST18-AU1 18.3.6 e-bus (y bsu) no parameter min (ns) typ (ns) max (ns) t55 eyrd low delay 2.85 t56 eyrd high delay 1.4 t57 eywr low delay 2.85 t58 eywr high delay 1.4 t59 ea valid delay t0+4.1 t60 ea hold time t0+4.05 t61 ed (in) setup time 9.2 t62 ed (in) hold time -7.55 t63 ed (out) valid delay (hi to lo z) 4.20 t64 ed (out) valid delay (lo to hi z) 2.05 clkout incycle eyrd ea ed (in) eywr ed (out) t59 t60 t55 t56 t57 t58 t61 t62 t63 t64
78/87 ST18-AU1 18.3.7 d950 control no parameter min (ns) typ (ns) max (ns) t65 reset setup time 8.30 t66 reset hold time t67 irq setup time 6 t68 irq min. pulse duration,low t69 lp setup time 6.2 t70 lp min. pulse duration,low t71 p (in) setup time 6.05 t72 p (in) hold time -5.85 t73 p (in) min pulse duration,low (edge t74 p (out ) low delay 2.6 t75 p (out ) high delay 3.0 clk0 clkout irq incycle p(in) p(out) t3 t4 t67 t71 t68 t74 reset lp t65 t66 t69 t70 t72 t75 t73
79/87 ST18-AU1 18.3.8 i2c host interface * = external r load to vdd = ** rise time defined by external rload no parameter min (ns) typ (ns) max (ns) t76 hda (in) setup time vs sclk 2xt0 + 1.1ns t77 hda (in) hold time vs sclk 0 t78* hda (out) low delay min 2xt0 + 6.45ns hda (out) low delay max 4xt0 + 6.45ns t79** hda (out) lo to hi z delay min tbd hda (out) lo to hi z delay max tbd t80 start condition setup tbd t81 stop condition setup tbd incycle scl (in) hda (in) t76 t77 t78 t79 hcl (in) hda (out) hda (out) clk0 2x t0 hcl (in) t80 t81
80/87 ST18-AU1 18.3.9 pcm and spdif * sclkpcm generated from clk1, prescaler divide by 2 no parameter min (ns) typ (ns) max (ns) t82* sclkpcm high delay 10.3 t83* sclkpcm low delay 10.4 t84 wspcm high delay 11.4 t85 wspcm low delay 11.30 t86 pcmout0/1/2 high delay 10.65 t87 pcmout0/1/2 low delay 10.60 t88 spdifout high delay 11.4 t89 spdifout low delay 11.3 clk1 sclk sclkpcm t9 t10 t82 t83 t84 t85 wspcm t86 t87 t88 t89 pcmout0/1/2 spdifout
81/87 ST18-AU1 18.3.10 i2s data input 0 * for this time, clkdin0 is halted by dreq0. no parameter min (ns) typ (ns) max (ns) t90 wsdin0 to clkdin0 setup time -1.45 t91 clkdin0 to wsdin0 hold time 2.10 t92 din0 to clkdin0 setup time -2.95 t93 clkdin0 to din0 hold time 3.45 t94 clkdin0 to dreq0 rise propagation time 7.05 t95* clk0 rise to dreq0 fall propagation time 12.90 t96 clk1 rise to clkdin0 fall propagation time 9.70 t97 clk1 rise to clkdin0 rise propagation time 9.90 t98 clk1 rise to wsdin0 fall propagation time 11 t99 clk1 rise to wsdin0 rise propagation time 10.95 t100 din0 to clk1 rise setup time -4.80 t101 clk1 rise to din0 hold time -5.40 t102 clk1 rise to dreq0 propagation time 10.90 clkdin0 wsdin0 din0 t90 t92 dreq0 t95 t94 t94 t95 slave mode clkdin0 wsdin0 din0 dreq0 master mode clk1 t96 t93 t92 t93 t97 t97 t96 t98 t99 t98 t99 t101 t100 t101 t100 t102 t102 t102 t102 t91 t90t91 t90 t91 t90 t91 t92 t93 t92 t93
82/87 ST18-AU1 18.3.11 i2s data input 1 no parameter min (ns) typ (ns) max (ns) t103 wsdin1 to clkdin1 setup time -1.6 t104 clkdin1 to wsdin1 hold time 1.4 t105 din1 to clkdin1 setup time -2.05 t106 clkdin1 to din1 hold time 2.35 t107 clk1 rise to clkdin1 fall propagation time 9.50 t108 clk1 rise to clkdin1 rise propagation time 9.50 t109 clk1 rise to wsdin1 fall propagation time 11.10 t110 clk1 rise to wsdin1 rise propagation time 11.15 t111 din1 to clk1 rise setup time -4.25 t112 clk1 rise to din1 hold time 4.56 clkdin1 wsdin1 din1 t103 t105 slave mode wsdin1 clkdin1 din1 master mode clk1 t107 t106 t105 t106 t108 t108 t107 t109 t110 t109 t110 t112 t111 t112 t111 t104 t103 t104 t103 t104 t103 t104 t105 t106 t105 t106
83/87 ST18-AU1 19 ST18-AU1 package specifications 19.1 ST18-AU1 package pinout the ST18-AU1 is available in a 160 pin plastic quad flat pack (pqfp) package. table 19.1 ST18-AU1 package pinout pin name pin no. pin name pin no. pin name pin no. pin name pin no. gnde 1 vdd 41 vdde 81 gnd 121 vdde 2 gnd 42 gnde 82 vdd 122 ide<15> 3 vdde 43 ea<0> 83 p<7> 123 ide<14> 4 gnde 44 ea<1> 84 p<6> 124 ide<13> 5 pcm_out0 45 ea_<2> 85 p<5> 125 ide<12> 6 pcm_out1 46 ea<3> 86 p<4> 126 ide<11> 7 pcm_out2 47 ea<4> 87 p<3> 127 ide<10> 8 wspcm 48 ea<5> 88 p<2> 128 ide<9> 9 sclkpcm 49 ea<6> 89 p<1> 129 ide<8> 10 spdifout 50 ea<7> 90 p<0> 130 ide<7> 11 irde 51 ea<8> 91 mode_reset 131 ide<6> 12 iwre 52 ea<9> 92 tdi 132 ide<5> 13 gnd 53 ea<10> 93 gnd 133 ide<4> 14 ibse 54 vdde 94 vdd 134 ide<3> 15 incycle 55 gnde 95 irq 135 ide<2> 16 clkout 56 ea<11> 96 lp 136 ide<1> 17 vdd 57 ea<12> 97 sclk 137 gnde 18 gnd 58 ea<13> 98 hsas 138 vdde 19 vdd 59 ea<14> 99 hda 139 vdd 20 gnd 60 ea<15> 100 hcl 140 ide<0> 21 mclk_mode 61 ed<0> 101 dreq0 141 iae<15> 22 clk0 62 ed<1> 102 clkdin1 142 gnd 23 clk1 63 ed<2> 103 clkdin0 143 iae<14> 24 clk0_mode 64 ed<3> 104 wsdin1 144 iae<13> 25 clk1_mode 65 ed<4> 105 wsdin0 145 iae<12> 26 pll_mode 66 vdde 106 din1 146 iae<11> 27 extal0 67 gnde 107 vdd 147 iae<10> 28 vdd 68 ed<5> 108 gnd 148 iae<9> 29 extal1 69 ed<6> 109 din0 149 iae<8> 30 xtal0 70 ed<7> 110 snap 150 iae<7> 31 xtal1 71 ed<8> 111 haltack 151 iae<6> 32 xbse 72 ed<9> 112 idle 152
84/87 ST18-AU1 19.2 160 pin pqfp package dimensions table 19.2 160 pin pqfp package dimensions iae<5> 33 xrde_exrd 73 ed<10> 113 erq 153 iae<4> 34 xwre_exwr 74 ed<11> 114 reset 154 iae<3> 35 eywr 75 ed<12> 115 tms 155 iae<2> 36 eiwr 76 ed<13> 115 tdo 156 iae<1> 37 eird 77 ed<14> 117 tck 157 iae<0> 38 eyrd 78 ed<15> 118 trst 158 gnde 39 vdd 79 vdde 119 gnd 159 vdde 40 gnd 80 gnde 120 vdd 160 ref. typ min max a 4,07 a1 0,25 a2 3,42 3,17 3,67 b 0,22 0,38 c 0,13 0,23 d 31,20 30,95 31,45 d1 28,00 27,90 28,10 d3 25,35 e 0,65 e 31,20 30,95 31,45 e1 28,00 27,90 28,10 e3 25,35 l 0,80 0,65 0,95 l1 1,60 k0 7 pin name pin no. pin name pin no. pin name pin no. pin name pin no.
85/87 ST18-AU1 figure 19.1 package diagram
86/87 ST18-AU1 20 device id the identification code for the ST18-AU1 is # m 52bd041, where m is a manufacturing revision number reserved by sgs-thomson. 21 ordering information for further information contact your local sgs-thomson sales office. bit 31 bit 0 mask rev st18 family variant sgs-thomson manufacturers id 1) 1) defined as 1 in ieee 1149.1 standard. reserved 0 1 0 1 0 0 1 0 1 0 1 1 1 1 0 1 0 0 0 0 0 1 0 0 0 0 0 1 52bd041 device package st18au1x??s 160 pin plastic quad flat pack (pqfp)
87/87 notes information furnished is believed to be accurate and reliable. however, sgs-th omson microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of sgs-tho mson microelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. sgs-tho mson microelectronics products are not authorized for use as critical components in life support devices or systems without the express writt en approval of sgs-thomson microelectronics. ? 1997 sgs-thoms on microelectronics - all rights reserved. sgs-thoms on microelectronics group of companies australia - brazil - canada - china - france - germany - italy - japan - korea - malaysia - malta - morocco - the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. 4

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